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Final Datasheet, Version 2.08, 2004-06-07
System Basis Chip TLE 6263
Integrated LS CAN, LDO and HS Switch
Automotive and Industrial
Never stop thinking.
CAN-LDO-ASIC
Final Datasheet
1 * * * * * * * * * * * * * * * * * * Features Standard fault tolerant differential CAN-transceiver Bus failure management Low power mode management Receive only mode for CAN CAN data transmission rate up to 125 kBaud Low-dropout voltage 5V regulator High side switch 2 wake-up inputs Power on and under-voltage reset generator Window watchdog Fail-safe output Early warning feature (VCC warning) Sense comparator input (VINT warning) Standard 8 bit SPI-interface Flash program mode Wide input voltage range Wide temperature range Enhanced power P-DSO-Package Ordering Code Q67007-A9465
TLE 6263
P-DSO-28-18 Enhanced Power
Type TLE 6263 G 2 Description
Package P-DSO-28-18
The TLE 6263 is a monolithic integrated circuit in an enhanced power P-DSO-28-18 package. The IC is optimized for use in advanced automotive electronic control units for body and convenience applications. To support this applications the TLE 6263 covers the main smart power functions such as failure tolerant low speed CAN-transceiver for differential mode data transmission, low dropout voltage regulator (LDO) for internal and external 5V supply as well as a SPI (serial peripheral interface) to control and monitor the IC. Further there are integrated additional features like a high side switch that can be used e.g. for cyclic supply of an external wake-up circuitry, two wake-up inputs, a window watchdog circuit with fail safe output as well as a reset and early warning feature. The IC is designed to withstand the severe conditions of automotive applications.
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3
Pin Configuration (top view)
TxD 1 RxD 2 RO 3 WK2 4 WK1 5 GND 6 GND 7 GND 8 GND 9 DO 10 CLK 11 CSN 12 DI 13 OUTHS 14
28 INT
P-DSO-28-6
(enhanced power package)
27 RTH 26 CANH 25 RTL 24 CANL 23 GND 22 GND 21 GND 20 GND 19 VCC 18 V CI 17 FSO 16 SI 15 VS
Figure 1:
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Pin Configuration TLE 6263 G (top view)
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4 Pin No. 1 2 3 4
Pin Definitions and Functions Symbol TxD RxD RO Function Transmit data input; integrated pull up; LOW: bus becomes dominant, HIGH: bus becomes recessive Receive data output; push-pull output; LOW: bus becomes dominant, HIGH: bus becomes recessive Reset output; open drain output, integrated pull up, active low Wake-Up input 2; for detection of external wake-up events, edge sensitive, in sleep mode monitored by cyclic sense feature when selected; weak pull up (2A) to avoid unwanted wake ups Wake-Up input 1; for detection of external wake-up events, edge sensitive, in sleep mode monitored by cyclic sense feature when selected; weak pull up (2A) to avoid unwanted weak ups Ground; to reduce thermal resistance place cooling areas on PCB close to this pins. SPI data output; this tri-state output transfers diagnosis data to the control device. Serial data transfered from DO is a 8 bit diagnosis word with the Least Significant Bit (LSB) transmitted first. The output will remain 3-stated unless the device is selected by a LOW on Chip-Select-Not (CSN). DO will accept data on the rising edge of CLK-signal; see table 4, 5, 6 for Diagnosis protocol SPI clock input; clocks the shiftregister; CLK has a pull down input, active HIGH, and requires CMOS logic level inputs SPI chip select not input; CSN is a pull up input, active LOW, serial communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal active pull up and requires CMOS logic level inputs SPI data input; receives serial data from the control device; serial data transmitted to DI is a 8 bit control word with the Least Significant Bit (LSB) being transferred first: the input has a pull down input, active HIGH, and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal; see table 3 for input data protocol High side switch output; controlled via SPI, in sleep mode controlled by internal cyclic sense function when selected
WK2
5
WK1
6, 7, 8, 9, GND 20, 21, 22, 23 10 DO
11 12
CLK CSN
13
DI
14
OUTHS
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4 Pin No. 15 16 17
Pin Definitions and Functions (cont'd) Symbol Function Power supply input; block to GND directly at the IC with ceramic capacitor Sense comparator input; for monitoring of external voltages, to program the detection level connect external voltage divider Fail safe output; to supervise and control critical applications, high when watchdog is correctly served, LOW at any reset condition, open drain output, internal pull up, active LOW Internal voltage supply; for stabilization of internal power supply, block to GND with an external capacitor CVI 100 nF Voltage regulator output; for 5V supply, to stabilize block to GND with an external capacitor CQ 100 nF CAN-L bus line; LOW in dominant state CANL-Termination output; connect to CANL bus line via termination resistor CAN-H bus line; HIGH in dominant state CANH-Termination input; connect to CANH bus line via termination resistor Interrupt output; to monitor wake-up events or valid sense input condition; integrated pull up resistor; active LOW
VS
SI FSO
18 19 24 25 26 27 28
VCI VCC CANL RTL CANH RTH
INT
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5
Functional Block Diagram
V BAT Charge Pump Drive + Protection
OUTHS
Vcc
CSN
SPI
CLK DI DO VCC
VCI Band Gap
Vcc
+
Time Base
Vcc
INT SI
Vs Vcc
Reset Generator + Watchdog
RO
Vcc
FSO
Vcc
Early Warning / V S supervisor CAN Standby / Sleep Control
Vcc
WK1 WK2
RTL CANH CANL RTH H Output Stage L Output Stage Fail Management Driver Temp Protect
Input Stage
Vcc
TxD
Vcc
Filter
Receiver
RxD
CAN Fail Detect
GND
Figure 2:
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TLE 6263 G Functional Bloc Diagram
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6
Circuit Description
The TLE 6263 is a monolithic IC, which incorporates a failure tolerant low speed CANtransceiver for differential mode data transmission, a low dropout voltage regulator for internal and external 5V supply as well as a SPI (serial peripheral interface) to control and monitor the IC. Further there are integrated a high side switch, two wake-up inputs, a window watchdog circuit with fail safe output as well as a reset circuit and early warning function. Figure 2 shows a schematic block diagram of the TLE 6263. Table 1 shows the status of the different chip features during the four main operation modes. Table 1: Truth table of the TLE 6263 Feature VCC Reset Watchdog Fail safe output VINT-Fail2) Sense input Wake-up 1 / 2 HS-switch4) HS-cyclic-sense4) SPI CAN transmit CAN receive RTL output RxD output INT output normal mode
ON ON ON ON ON ON ON3) ON OFF ON ON ON switched to Vcc L = bus dominant; H = bus recessive active low early warning
receive-only mode
ON ON ON ON ON ON ON3) ON OFF ON OFF ON switched to Vcc L = bus dominant; H = bus recessive active low early warning for VINT and VCC
Vbat stand-by mode
ON ON ON ON
1) 5)
sleep mode
OFF OFF OFF OFF ON OFF ON OFF ON OFF OFF OFF switched to Vs low low
ON ON ON ON ON ON OFF OFF switched to Vs active low wake-up interrupt active low early warning
1) 2) 3)
at low VCC output current only active when watchdog undercurrent function is not activated
can only be monitored in Vbat-stand-by mode via SPI no wake-up interrupt generated, logic level status monitored via SPI 4) only active when selected via SPI
5)
if watchdog under-current function active, than FSO = low
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6.1
Operation Modes
The TLE 6263 offers four different operation modes that are controlled via the SPI interface (NSTB= SPI Input Bit3, ENT=SPI Input Bit2): the normal operation mode, the receive-only mode, the Vbat stand-by mode and the sleep operation mode. Please see the state diagram (figure 3). Normal and Receive only Mode In the normal operation mode both is possible, receiving and transmitting of messages, in the receive-only mode (RxD-only mode) the output stages are disabled which doesn't allow the CAN controller to send a message to the bus. In the state diagram (figure 3), VCC is the status of the voltage regulator.
SPI Input Bits: IBit2 = ENT IBit3 = NSTB
NSTB 1
Power Down
Start Up Power Up
Normal Mode ENT 1 VCC ON
2) NSTB
ENT
1 1
2) NSTB ENT or VCC
0 0 VRT
2)
ENT
0
2)
ENT
1
RxD-Only NSTB 1 ENT 0
0 1
2) NSTB or VCC
0 VRT 1
Vbat Stand-By NSTB 0 ENT 0 VCC ON
1)
after 500s
HS cyclic sense NSTB 0 ENT 1 VCC ON
2) NSTB
0
VCC ON
2) NSTB
2) NSTB 2) ENT
RxD = LOW if a wake up occured by WK1, WK2 or CAN message
1)
after 64ms
HS Switch = ON
Vbat Stand-By Mode
Sleep Mode
Sleep NSTB 0 ENT 1 VCC OFF
Wake Up = transition on WK1 or WK 2 for t > tWU or CAN message
2)
ENT
1
HS switch = OFF
1)
after 64ms
1)
after 500s
HS cyclic sense NSTB 0 ENT 1 VCC OFF
1)
automatic repeated transition only if HS cycl sense feature is selected by SPI IBit 4 NSTB and ENT are both SPI Input Bits (IBits)
HS Switch = ON
2)
Figure 3:
State Diagram
Vbat stand-by mode and sleep mode In the Vbat stand-by mode and sleep mode the RTL output voltage is switched to VS. Both modes are low power modes. In the sleep mode the whole application is switched
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off by disabling the voltage regulator. That allows the total current consumption to drop down to less than 100 A. When a reset occurs, due to false watchdog triggering, the TLE6263 automatically switches from normal mode or receive-only mode respectively, to the Vbat stand-by mode. If a watchdog reset occurs in the Vbat stand-by mode the IC remains in this mode. In sleep mode a wake-up at any of the wake-up inputs as well as via the bus lines (CANH or CANL) automatically sets the TLE 6263 in Vbat stand-by mode. In the Vbat stand-by mode a wake-up is monitored by setting the output RxD low. This feature works as a flag, to indicate a wake event to the microcontroller. To send and to receive messages, the CAN-transceiver has to be set to normal operation mode by the microcontroller. In case the IC shall directly be set back to sleep mode after a wake-up, an internal wakeflip-flop has to be reseted via the SPI. Therefore IBIT1 has to be set high and then low again by a second SPI transmission. A transition from the Vbat stand-by mode to the normal mode or receive-only mode respectively, automatically resets the wake-flip-flop. 6.2 Low Dropout Voltage Regulator
The integrated low dropout voltage regulator is able to drive the internal loads (e.g. CAN-circuit) as well as external 5V loads. Its output voltage tolerance is better than 2%. The maximum output current is limited to 110 mA. An external reverse current protection is recommended at the pin Vs to prevent the output capacitor from being discharged by negative transients or low input voltage. Stability of the output voltage is guaranteed for output capacitors CQ 100 nF, nevertheless it is recommended to use capacitors CQ 10 F to buffer the output voltage and therefore improve the reset behavior at input voltage transients. To stabilize the internal supply a capacitor CVI 100 nF directly connected to the pin VCI is required. 6.3 CAN Transceiver
The TLE 6263 is optimized for low speed data transmission up to 125 kBaud in automotive applications. Figure 4 shows the principle configuration of a CAN network.Normally a differential signal is transmitted and received respectively. When a bus wiring failure (see table 2) is detected the device automatically switches to a dedicated CANH or CANL single-wire mode to maintain the communication if necessary. Further a receive-only mode is implemented that allows a separate CAN node diagnosis. During normal and RxD-only mode, RTL is switched to VCC and RTH to GND. During Vbat stand-by and the cyclic wake mode, RTL is switched to VS and RTH to GND.
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Controller 1 RxD1 TxD1 RxD2
Controller 2 TxD2
Transceiver1
Transceiver2
BUS Line
Figure 4:
CAN Network Example
Receive-only Mode The receive only mode is designed for a special test procedure to check the bus connections. Figure 5 shows a network consisting of 5 nodes. If the connection between node 1 and node 3 shall be tested, the nodes 2,4 and 5 are switched into receive only mode. Node 1 and node 3 are in normal mode. If node 1 sends a message, node 3 is the only node which can acknowledge the message, the other nodes can only listen but cannot send an acknowledge bit. If node 1 receives the acknowledge bit from node 3, the connection is OK.
5 4
1
3 2
Figure 5:
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Testing the Bus Connection in Receive-only Mode
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Electromagnetic Emmision (EME) To reduce radiated electromagnetic emission (EME), the dynamic slopes of the CANL and CANH signals are both limited and symmetric. This allows the use of an unshielded twisted or parallel pair of wires for the bus. During single-wire transmission (one of the bus lines is affected by a bus line failure) the EME performance of the system is degraded from the differential mode. 6.4 Bus Failure Management
There are 9 different CAN bus wiring failures defined by the ISO 11519-2/ISO 11898-3 standard. These failures are devided into 7 failure groups (see Table 2). The difference between ISO11898-3 and ISO 11519-2 is also shown in Table 2. When a bus wiring failure is detected the device automatically switches to a dedicated CANH or CANL single-wire mode to maintain the communication if necessary. Therefore it is equipped with one differential receiver and four single ended comparators (two for each bus line). To avoid false triggering by external RF influences, the single wire modes are activated after a certain delay time. As soon as the bus failure disappears the transceiver switches back to differential mode after another time delay. The differential receiver threshold is set to typ. -2.5V. This ensures correct reception in the normal operation mode as well as in the failure cases 1, 2, 3a(6a) and 4(5) with a noise margin as high as possible. When one of the bus failures 3(6), 5(4), 6(3), 6a(3a), and 7 is detected, the defective bus wire is disabled by switching off the affected bus termination and output stage. The failure cases in brackets() are the failure cases according to ISO 11898-3. Simultaneously the multiplexing output of the receiver circuit is switched to the unaffected single ended comparator The bus failures are monitored via the diagnosis protocoll of the SPI. A general indication of a CAN failure during normal mode at CANH or CANL is reported by OBIT 4 and 5. It is also possible to distinguish 6 CAN bus failures or failure groups on the SPI output bits 3 to 7 in the RxOnly mode(see Table 2 and 5). The failures are reported until transmission of the next CAN word begins. In case the transmission data input TxD is permanently dominant, both, the CANH and CANL transmitting stage are disabled after a certain delay time tTxD. This is necessary to prevent the bus from being blocked by a defective protocol unit or short to GND at the TxD input. In order to protect the transceiver output stages from being damaged by shorts on the bus lines, current limiting circuits are integrated. The CANL and CANH output stage respectively are protected by an additional temperature sensor, that disables them as soon as the junction temperature exceeds the maximum value. In the temperature shutdown condition of the CAN output stages receiving messages from the bus lines is still possible.
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Table 2: CAN bus line failure cases failure # 1 2 3 3a 4 5 6 6a 7 6.5 failure description according to ISO 11898-3 CANH line interrupted CANL line interrupted CANH shorted to Vbat CANH shorted to Vcc CANL shorted to GND CANH shorted to GND CANL shorted to Vbat CANL shorted to Vcc CANL shorted to CANH SPI (serial peripheral interface) failure description according to 11519-2 CANL line interrupted CANH line interrupted CANL shorted to Vbat CANL shorted to Vcc CANH shorted to GND CANL shorted to GND CANH shorted to Vbat CANH shorted to Vcc CANL shorted to CANH
The 8-bit wide programming word (input word, see table 3) is read in via the data input DI, and this is synchronized with the clock input CLK supplied by the C. The diagnostic information depends on the operation mode. The internal latches for the Vbat-stand-by diagnosis are reseted when leaving this mode. Table 3, Input Data Protocol all modes IBIT 7 6 5 4 3 2 1 0 H = ON L = OFF Watchdog Undercurrent Control Set VINT-Fail + VCC Fail Flag OUTHS ON OUTHS Cyclic Sense Not Standby Enable Transmit Reset Internal WK-FF Watchdog Trigger Table 4, Diagnosis Data Protocol normal mode OBIT 7 6 5 4 3 2 1 0 H = ON L = OFF HS UV / Temp-Shut Down HS Overcurrent CANL bus fail CANH bus fail WK2 logic level WK1 logic level Window Watchdog Reset Temperature Prewarning
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The transmission cycle begins when the TLE6263 is selected by the chip select not input CSN (H to L). After the CSN input returns from L to H, the word that has been read in becomes the new control word. The DO output switches to tri-state status at this point, thereby releasing the DO bus circuit for other uses. For details of the SPI timing please refer to figure 6 to 9. Table 5, Diagnosis Data Protocol RxD-only mode OBIT 7 6 5 4 3 2 1 0 CAN Failure 5(4) and 7 CAN Failure 6 (3) CAN Failure 6a (3a) CAN Failure 2(1) and 4(5) CAN Failure 3(6) CAN Failure 1(2) and 3a(6a) Window Watchdog Reset Temperature Prewarning Table 6, Diagnosis Data Protocol Vbat-Stand-by mode OBIT 7 6 5 4 3 2 1 0 H = ON L = OFF VCC Not-Fail VINT Not-Fail WK1/2 Initialization Fail Wake via CAN bus lines WK2 voltage level WK1 voltage level Window Watchdog Reset Temperature Prewarning
H = ON L = OFF ()... values in brackets according to ISO11898-3 see table 2
6.6
Window Watchdog, Reset
When the input voltage exceeds the reset threshold voltage the reset output RO is switched HIGH after a delay time of typ. 8ms. This is necessary for a defined start of the microcontroller when the application is switched on. As soon as an under-voltage condition of the output voltage (VCC < VRT) appears, the reset output RO is switched LOW again (power on and under-voltage reset). The LOW signal is guaranteed down to an output voltage VQ 1V. Please refer to figure 13, Reset Timing Diagram. In sleep operation mode, the watchdog circuit is automatically disabled. Long Open Window After the above described delayed reset (LOW to HIGH transition of RO) the window watchdog circuit is started by opening a long open window of typ. 65ms. The long open window allows the microcontroller to run his set-up and then to trigger the watchdog via the SPI, refer to figure 11,Watchdog Timeout Definitions. Within the long open window
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period a watchdog trigger is detected as a "rising edge" by sampling a HIGH on the IBIT 0. The trigger is accepted when the CSN input becomes HIGH after the transmission of the SPI word. After each reset as well as after a power on condition the default value of IBIT 0 is LOW. Closed and Open Window A correct watchdog trigger results in starting the window watchdog by opening a closed window of typ. 6 ms followed by a open window of typ. 10 ms. From now on the microcontroller has to service the watchdog trigger by inverting the IBIT 0 alternating. The "negative" or "positive" edge has to meet the open window time. A correct watchdog service immediately results in starting the next closed window. Please refer to figure 12, Watchdog Timing Diagram. Watchdog Reset Should the trigger signal not meet the open window a watchdog reset is created by setting the reset output RO low for a period of typ. 2 ms. Then the watchdog starts again by opening a long open window. In addition, the SPI OBIT 1 (diagnosis bit 1) is set HIGH until the next successful watchdog trigger to monitor a watchdog reset. OBIT1 is also HIGH until the watchdog is correctly triggered after power-up / start-up. For fail safe reasons the TLE6263 is automatically switched in Vbat-stand-by mode if a watchdog trigger failure occurs. So the power consumption can be minimized in case of a permanent faulty microcontroller. In case of either an undervoltage reset or a watchdog reset all SPI input registers (IBIT 0 to IBIT 7) are set low. Undercurrent Disabling Function To avoid cyclic wake-up's of the microcontroller due to missing watchdog pulses when the microcontroller is in a low power mode, an automatic undercurrent disabling function of the watchdog circuit can be selected for the TLE 6263 Vbat-stand-by mode. For activation of this feature, the VCC output current in the Vbat-stand-by mode has to be less than the undercurrent threshold (ICC < ICCWD) and in addition the SPI IBIT 7 has to be set HIGH. When the microcontroller returns back to normal mode or the output current becomes higher than ICC > ICCWD the watchdog circuit is enabled again. A long open window is started then, to ensure a simple synchronization of the watchdog timing to the watchdog services of the microcontroller. 6.7 Flash program mode
To disable the watchdog feature a flash program mode is available. This mode is selected by applying a voltage of 6.8V < VINT < 7.2V at pin INT. This is useful e.g. if the flash-memory of the micro has to be programmed and therefore a regular watchdog triggering is not possible. If the SPI is required in the flash program mode to change e.g. the mode of the TLE6263 the first input telegram has to be "00000000".
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6.8
Fail Safe feature
The output FSO becomes HIGH when the watchdog is correctly serviced by the microcontroller for the fourth time. As soon as either an under-voltage reset or watchdog reset occurs, it is set LOW again. This feature is very useful to control critical applications independent of the due function of the microcontroller e.g. to disable the power supply in case of a microcontroller failure. 6.9 Sense Comparator (pin SI) and VINT-fail
The sense comparator (early warning function) compares a voltage defined by the user to an internal reference voltage. Therefore the voltage to be supervised has to be scaled down by an external voltage divider in order to compare it to the internal sense threshold VSIth. This feature can be used e.g. to supervise the battery voltage in front of the reverse protection diode. The microcontroller is given a pre-warning before an under-voltage reset due to low input voltage occurs. The pre-warning is flagged by setting the interrupt output INT low in normal mode, receive only mode and Vbat-stand-by mode. In sleep operation mode the sense function is inactive. Calculation of the voltage divider can be easily done since the sense input current can be neglected. An internal blanking time prevents from false triggering due to line transients. Further improvement is possible by the use of an external ceramic capacitor switched between SI and GND (see Application Diagram Figure 15). 6.10 VINT- and VCC-fail flag
To activate the VINT supervisor feature the SPI IBIT 6 has to be set HIGH to set an internal flip-flop. This automatically sets the Vbat-stand-by OBIT 6 HIGH, too. Should the internal supply voltage become lower than the internal threshold VVINT,th (typ. 2.5V) the NOT VINT-Fail bit becomes LOW to indicate the low voltage condition. All SPI input registers are set LOW due to a low voltage condition of the internal supply voltage. Like the wake-up diagnosis the VINT-Fail diagnosis can only be monitored in the Vbatstand-by mode. The VINT-Fail feature can also be used to give an indication when the ECU has been changed and therefore a pre-setting routine of the microcontroller has to be started. Further to the reset threshold there is another supervisor threshold implemented, to monitor the output voltage VCC. This threshold is called VVCC,th (typ. 2.5V). The NOT VCC-Fail feature is monitored via OBIT 7 in the Vbat-stand-by mode and set, like the NOT VINT-Fail flag, via IBIT 6 (so both fail features are activated with the IBIT 6 but monitored via OBIT 6 and OBIT 7 during Vbat-stand-by). In the receive-only mode both fail bits cause the interrupt output INT to go low.
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6.11
Wake-Up Inputs WK1, WK2
In addition to a wake-up from sleep mode via the bus lines CANH or CANL it is also possible to wake-up the TLE6263 from low power mode via the wake-up inputs WK1 and WK2. The wake-up inputs are sensitive to a transition of the voltage level, either from high to low or the other way round. They are active in all operation modes. In the normal mode the current logic level at WK1/2 is monitored via the SPI (see table 4 and 6). A positive or negative voltage edge at WK1/2 in Vbat-stand-by mode or sleep mode immediately results in setting the output RxD low to signal a wake-up. After a wake-up via WK1/2 the transmission of the SPI diagnosis word in the Vbat-stand-by mode shows the logic level that has caused the wake-up. To get the current voltage levels at WK1/2 in the Vbat-stand-by mode the internal wake flip-flop has to be reseted by the IBIT1 for each transmission. As long as IBIT1 is set high or the internal wake flip-flop is reseted respectively, in the Vbat-stand-by mode the RxD output is blocked to signal a new wakeup event via the CAN-bus or the wake-up inputs. Further to the continues sensing at the wake-up inputs a cyclic sense feature is possible. When the OUTHS cyclic sense feature is selected via the SPI IBIT 4 the high side switch as well as the WK1/2 inputs are periodically activated by the TLE6263 in the sleep and Vbat-stand-by mode. When switching the TLE6263 into sleep mode (cyclic sense feature activated) the voltage level at the wake-inputs is sensed 2 times to initialize the reference voltage. Should this initialisation fail (2 samples are unequal) the device is automatically set in Vbat-stand-by mode and the initialisation error is shown on the OBIT 5. To enter the sleep mode now directly from the Vbat-stand-by mode, the internal wake flip-flop has to be reseted by the IBIT 1. 6.12 Interrupt output INT
Like the reset output, the interrupt output is a low active output. It is used to monitor low voltage conditions at the sense input in normal mode and stand-by mode (see table 8). In the receive-only mode the VINT-fail flag and VCC supervisor are monitored. 6.13 High Side Switch
The high side output OUTHS is able to switch loads up to 150 mA. Its on-resistance is 1.0 typ. @ 25C. This switch is controlled via the SPI input bits 4 and 5. In normal mode, receive-only mode and Vbat-stand-by mode the high side output is switched on and off, respectively via the SPI input bit 5. To supply external wake-up circuits in sleep mode and Vbat-stand-by mode the output OUTHS can be periodically switched on by the TLE6263 itself. In order to activate this cyclic sense feature the SPI IBIT 4 has to be set high. The auto-timing period then is typ. 65 ms, the on-time is typ. 1 ms. Should there be any over-current condition at the switch in the sleep mode (cyclic sense activated) or Vbat-stand-by mode a wake-up is flagged
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via the RxD output. The over-current condition is monitored on the SPI OBIT 6 in normal operation mode. The SPI OBIT 0 flags a thermal pre-warning of the high side switch. By this the microcontroller is able to reduce the power dissipation of the TLE6263 by switching off functions of minor priority until the temperature threshold of the thermal shutdown is reached. Further OUTHS is protected against short circuit and overload. As soon as the under-voltage condition of the supply voltage is met (VS < VUVOFF), the switch is automatically disabled by the under-voltage lockout circuit. Moreover the switch is automatically disabled when a reset or watchdog reset occurs. 6.14 Hints for unused pins
SI: connect to VS OUTHS: leave open WK1/2: connect to VS or leave open INT: leave open RO: leave open FSO: leave open SI: switch to Vs
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7 7.1
Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. Unit Remarks
Parameter
Voltages Supply voltage Supply voltage Regulator output voltage CAN bus voltage (CANH, CANL) CAN bus voltage (CANH, CANL)
VS VS VCC VCANH/L VCANH/L
-0.3 -0.3 -0.3 -20 -40 -0.3 -0.3 -0.3 -40 -3
28 40 5.5 28 40
V V V V V V V V V kV
human body model, C = 100 pF, R = 1.5 k human body model, C = 100 pF, R = 1.5 k VS >0 V tp< 0.5s; tp/T < 0.1 0 V < VS < 24 V 0 V < VCC < 5.5 V 0 V < VS < 24 V 0 V < VCC < 5.5 V 0 V < VS < 24 V 0 V < VCC < 5.5 V tp< 0.5s; tp/T < 0.1
Logic input voltages (DI, CLK, VI CSN, OSC, TxD) Logic output voltage (DO, RO, INT, RxD, FSO) Termination input voltage (RTH, RTL) Input voltages at WK1/2 and SI Electrostatic discharge voltage at pin CANH, CANL, GND, VS Electrostatic discharge voltage at any other pin
VCC
+0.3
VDRI,RD VTL /TH VWK/SI Vesd
VCC
+0.3
VS
+0.3 40 3
Vesd
-1
1
kV
Currents Output current; Vcc Output current; OUTHS
ICC IOUTH1
-
1)
- 0.2
A A
1) 1)
internally limited internally limited
Note 1): Not subject to production test - specified by design
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7.1
Absolute Maximum Ratings (cont'd) Symbol Limit Values min. max. Unit Remarks
Parameter
Temperatures Junction temperature Storage temperature
Note:
Tj Tstg
- 40 - 50
150 150
C C
- -
Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
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7.2
Operating Range Symbol Limit Values min. max. V V V/s V nF 460 1.5 - 40 150 nF MHz C
After VS rising above VUV ON thermally limited
Parameter Supply voltage Supply voltage Supply voltage slew rate Logic input voltage (DI, CLK, CSN, TxD) Output capacitor Output capacitor SPI clock frequency Junction temperature Thermal Resistances Junction pin Junction ambient
Note:
Unit
Remarks
VS VS
dVS /dt
VUV OFF 20 VUV OFF 40
-0.5 - 0.3 100 100 5
VI CCC CVI fclk Tj
VCC
Rthj-pin Rthj-a
- -
25 65
K/W K/W
Calculation of the junction temperature Tj = Tamb + P x Rthj-a
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7.3
Electrical Characteristics
VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C (max. 125C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Quiescent current Pin VS Current consumption
IQ = IS - ICC
Current consumption
IQ IQ IQ IQ IQ
- - - -
5.5 8 300 50
10 10 400 80 3
mA mA A A mA
normal mode; ICC = 30 mA; TxD recessive normal mode; ICC = 30 mA; TxD dominant stand-by mode; Tj=25C; ICC = 1 mA; Ibit 7 = H sleep mode; Tj=25C; SPI Ibit 4 = L; VCC = VCCI = 0 V OUTHS active; SPI Ibit 4 = H; sleep mode; VCC = VCCI = 0 V
IQ = IS - ICC
Current consumption
IQ = IS - ICC
Current consumption Current consumption
Voltage Regulator; Pin VCC Output voltage Output voltage Line regulation Load regulation
VCC VCC VCC VCC
4.9 4.8
5.0 5.0
5.1 5.2 50 50
V V mV mV dB mA mA
0.1 mA< ICC< 100 mA 6 V< VI< 20 V 0A < ICC < 100 A 6 V < VS < 16 V; ICC = 1mA 5mA< ICC< 100mA; VS = 6V VS < 1 Vss; CQ 10F 100Hz< f <100kHz note 1) VCC = 0 V ICC = 80 mA; note 1)
Power supply ripple rejection PSRR Output current limit Output current limit Drop voltage
40 110 120 120 0.5
VDR = VS - VCC
ICCmax ICCmax VDR
V
note 1) measured when the output voltage VCC has dropped 100 mV from the nominal value obtained at 13.5 V input voltage VS
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7.3
Electrical Characteristics (cont'd)
VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C (max. 125C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Oscillator internal oscillating frequency fOSC Internal cycling time (1/64 * fOSC)-1 Internal cycling time (1/64 * fOSC)-1 Reset Generator; Pin RO Reset threshold voltage Reset low output voltage 125 0.43 0.30 0.51 0.51 0.64 0.72 kHz ms ms
sleep mode
tCYL tCYL
VRT VRO
4.5
4.65 0.2
4.8 0.4
V V
VCC decreasing IRO = 1mA for VCC = VRT or IRO = 200 A for VCC 1V
Reset high output voltage Reset pull up current Reset reaction time Reset delay time (16 cyl.) Watchdog Generator
VRO IRO tRR tRD
4.0 20 1 6.9 200 2 8.5
VCC+ V
0.1 500 10 12 A s ms
VRO = 0V VCC < VRT to RO = L
tWD Long open window (128 cyl.) tLW Closed window (12 cyl.) tCW tOW Open window (20 cyl.) Watchdog reset-puls time tWDR
Watchdog trigger (4 cyl.) Watchdog undercurrent disable threshold
7.2 55 5.1 8.6 1.7 0.5
10 65 6.1 10.2 2 4
13.6 81 7.7 13 3 7
ms ms ms ms ms mA
Tj < 85 C; Watchdog OFF when ICC < ICCWD and SPIIbit 7= H
ICCWD
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7.3
Electrical Characteristics (cont'd)
VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C (max. 125C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Watchdog Undercurrent disable hysteresis Watchdog Undercurrent reaction time Fail Safe Output; Pin FSO Watchdog edge count difference to set HIGH Fail Safe low output voltage
Symbol
Limit Values min. typ. 0.5 8 max.
Unit Test Condition mA s
Tj=25C
ICCWDhys tLHR
nFS
4 0.2 0.4
V V
IFSO= 1mA for VCC = VRT or IFSO = 200 A for VCC 1V IFSO= -1mA for VCC VRT
VFS
Fail Safe high output voltage VFS
4.0
VCC+ V
0.1
Sense Input (Early Warning) SI, VINT-Fail, Interrupt Output INT Sense In threshold voltage Sense In threshold hysteresis Sense Input Current Sense reaction time Interrupt Out high voltage Interrupt Out low voltage Interrupt pull up current VCC-Fail threshold voltage VCC-Fail reaction time VINT-Fail threshold voltage
VSI,th VSI,hys ISI tS,r VINThigh VINTlow IINT VVCC,th tVCC,r VVINT,th
2.1
2.3 200 0.1
2.5
V mV A
VSI decreasing until INT transition to LOW
VSI 0 V VS < VS,th to INT = low I0 = - 20 A I0 = 1.25 mA VINT = 0V
5 0.7 x
10 - - 150 2.8 5
20
s V V A V s
VCC
0 20 2.3
VCC
0.9 500 3.1
VCC < VVCC,th to Obit 6 = low; Vbatstand-by mode proportional to VS
1.5
3.2
4.3
V
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7.3
Electrical Characteristics (cont'd)
VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C (max. 125C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Wake-Up Inputs WK1 / WK2 Wake-up threshold voltage Minimum time for wake-up Input current
VWUth tWU IWK
2 10
3 15 -2
4 32
V s A
sleep mode; Vbatstand-by mode sleep mode; Vbatstand-by mode VWK = 0 V
High Side Output OUTHS; (controlled by bit 4 and bit 5 of SPI input word) Static Drain-Source ON-Resistance; IOUTH3 = - 0.15 A Active zener voltage
RDSON HS -
1.0 - 2.5 -
1.5 3.0 3.0 5.0 1
V V A s s
Tj = 25 C
5.2 V VS 9 V Tj = 25 C 5.2 V VS 9 V IOUTHS = - 0.15 A IOUTHS = 0.15 A VOUTHS = 0 V CSN high to OUTHS CSN high to OUTHS -
VOUTHS Clamp diode forward voltage VOUTHS Leakage current IQLHS Switch ON delay time tdONHS Switch OFF delay time tdOFFHS Overcurrent shutdown ISDHS
threshold Shutdown delay time Current limit UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis Cyclic sense period (128 cyl.)
-2 -4 20 20
- 0.8 - 0.3 - 0.2 A 10 - 4.5 - 38 35 5.2 4.7 0.5 65 50 6.0 5.2 - 92 s V V V ms
tdSDHS IOCLHS VUV ON VUV OFF VUV HY tP CS
- 1.2 - 0.6 - 0.3 A
VS increasing VS decreasing VUV ON - VUV OFF sleep mode SPI-bit 4 = H,
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7.3
Electrical Characteristics (cont'd)
VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C (max. 125C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Cyclic sense period (128 cyl.) Cyclic sense ON time (1 cyl.) CAN-Transceiver Receiver Output RxD HIGH level output voltage LOW level output voltage Transmission Input TxD HIGH level input voltage threshold LOW level input voltage threshold HIGH level input current LOW level input current Bus Lines CANL, CANH Differential receiver recessive-to-dominant threshold voltage Differential receiver dominant-to-recessive threshold voltage CANH recessive output voltage
Symbol
Limit Values min. typ. 65 max. 80 55
Unit Test Condition ms
Vbat-stand-by mode; SPI-bit 4 = H; watchdog undercurrent feature active
tP CS
tCS on
0.5
ms
VOH VOL
VCC
-0.9 0
VCC
0.9
V V
I0 = -250 A I0 = 1.25 mA
VIH VIL IIH IIL VCC
0.52x 0.7 x V
VCC VCC
VCC
0.3 x 0.48x -150 -600 -30 -300 -10 -40
V A A
Vi = 4 V Vi = 1 V
VdRxDrd -2.8 VdRxDdr -3.1 VCANHr
-2.5
-2.2
V
-2.9
-2.5
V
0.1
0.2
0.3
V
TxD = VCC; RRTH < 4 k
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7.3
Electrical Characteristics (cont'd)
VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C (max. 125C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter CANL recessive output voltage CANH dominant output voltage CANL dominant output voltage CANH output current
Symbol
Limit Values min. typ. max.
Unit Test Condition V
TxD = VCC; RRTL < 4 k TxD = 0 V; ICANH = - 40 mA TxD = 0 V; ICANL = 40 mA VCANH = 0 V; TxD = 0 V sleep mode; VCANH = 12 V VCANL = 5 V; TxD = 0 V sleep mode; VCANL = 0 V
VCANLr
VCC
-0.2
VCANHd VCC VCANLd ICANH
-1.4
VCC
1.0
-1.0
VCC
1.4 -50 5
V V mA A mA A V
-110 -5
-80
CANL output current
ICANL
50 -5
80
110 5
Voltage detection threshold Vdet(th) for short-circuit to battery voltage on CANH and CANL CANH wake-up voltage threshold CANL wake-up voltage threshold
6.5
7.3
8.0
VH,wk VL,wk
1.2 2.2 1.6 2.4 -5 -5
1.9 3.1 2.1 2.9
2.7 3.9 2.6 3.4 5 5
V V V V A A
low power modes
low power modes
CANH single-ended receiver VCANH threshold CANL single-ended receiver threshold CANL leakage current CANH leakage current
failure cases 3, 5, 7 recessive to dominant failure case 6 and 6a recessive to dominant VCC = 0 V, VS = 0 V, VCANL = 13.5 V VCC = 0 V, VS = 0 V, VCANH = 5 V
VCANL ICANLl ICANHl
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7.3
Electrical Characteristics (cont'd)
VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C (max. 125C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Termination Outputs RTL, RTH RTL to VCC switch-on resistance RTL to BAT switch series resistance RTH to ground switch-on resistance RTH output voltage RTH pull-down current RTL pull-up current RTH leakage current RTL leakage current
RRTL RoRTL RRTH VoRTH IRTHpd IRTLpu IRTHl IRTLl
40 -120 -5 -5 5
40 15 40 0.7 75 -75
95 30 95 1.0 120 -40 5 5
k V A A A A
Io = - 10 mA;
VBAT-stand-by or sleep mode
Io = 10 mA; Io = 1 mA; sleep mode or VBAT-stand-by
failure cases 6 and 6a failure cases 3, 3a, 5 and 7 VCC = 0 V, VS = 0 V, VRTH = 5 V, Tj < 85 C VCC = 0 V, VS = 0 V VRTL = 13.5 V, Tj < 85 C
CAN-Transceiver Dynamic Characteristics CANH and CANL bus output trd transition time recessive-todominant CANH and CANL bus output tdr transition time dominant-torecessive Minimum dominant time for wake-up on CANL or CANH 0.6 1.2 2.1 s
10% to 90%; C1 = 10 nF; C2 = 0; R1 = 100 10% to 90%; C1 = 1 nF; C2 = 0; R1 = 100 Stand-by modes
0.3
0.6
1.3
s
twu(min)
12
20
32
s
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7.3
Electrical Characteristics (cont'd)
VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C (max. 125C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Failure cases 3 and 6 detection time Failure case 6a detection time Failure cases 5 and 7 detection time Failure cases 5, 6, 6a and 7 recovery time Failure cases 3 recovery time Failure cases 5 and 7 detection time Failure cases 6 and 6a detection time Failure cases 5, 6, 6a and 7 recovery time
Symbol
Limit Values min. typ. 45 4.8 2.0 45 500 1.0 4.0 1.0 1.5 max. 80 8.0 4.0 80 750 2.4 8.0 2.4 2.1 25 2.0 1.0 25 250
Unit Test Condition s ms ms ms s ms ms ms s
Stand-by modes
tfail
tfail
0.4 0.8 0.4 -
Stand-by modes
Stand-by modes
Propagation delay tPD(L) TxD-to-RxD LOW (recessive to dominant)
C1 = 100 pF; C2 = 0; R1 = 100 ; no failures and bus failure cases 1, 2, 3a and 4 C1 = C2 = 3.3 nF; R1 = 100 ; no bus failure and failure cases 1, 2, 3a and 4 C1 100 pF; C2 = 0; R1 = 100 ; bus failure cases 3, 5, 6, 6a and 7 C1 = C2 = 3.3 nF; R1 =100 ; bus failure cases 3, 5, 6, 6a and 7
-
1.7
2.4
s
- -
1.8 2.0
2.5 2.6
s s
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7.3
Electrical Characteristics (cont'd)
VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C (max. 125C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol -
Limit Values min. typ. 1.3 max. 2.0
Unit Test Condition s
C1 = 100 pF; C2 = 0; R1 =100 ; no failures and bus failure cases 1, 2, 3a and 4 C1 = C2 = 3.3 nF; R1 = 100 ; no bus failure and failure cases 1, 2, 3a and 4 C1 100 pF; C2 = 0; R1 = 100 ; bus failure cases 3, 5, 6, 6a and 7 C1 = C2 = 3.3 nF; R1 = 100 ; bus failure cases 3, 5, 6, 6a and 7
Propagation delay tPD(H) TxD-to-RxD HIGH (dominant to recessive)
-
2.5
3.5
s
- - Edge-count difference ne (falling edge) between CANH and CANL for failure cases 1, 2, 3a and 4 detection Edge-count difference (rising edge) between CANH and CANL for failure cases 1, 2, 3a and 4 recovery TxD permanent dominant disable time SPI-Interface Logic Inputs DI, CLK and CSN H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull up current at pin CSN -
1.3 1.7 4
2.1 2.6 -
s s -
-
2
-
-
tTxD
1.3
2.0
3.5
ms
VIH VIL VIHY IICSN
- 0.3 x
- - 200
0.7 x
V V mV A
- - - VCSN = 0.7 x VCC
VCC
- 500 -5
VCC
50 - 100 - 25
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7.3
Electrical Characteristics (cont'd)
VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C (max. 125C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Pull down current at pin DI and CLK Input capacitance at pin CSN, DI or CLK
Symbol
Limit Values min. typ. 25 10 max. 100 15 5 -
Unit Test Condition A pF
VDI = 0.2 x VCC
Not subject to production test specified by design
IICLK/DI CI
Logic Output DO H-output voltage level L-output voltage level Tri-state leakage current Tri-state input capacitance
VDOH VDOL IDOLK CDO
VCC
- - 10 -
VCC
0.2 - 10
- 0.4 10 15
V V A pF
IDOH = 1 mA IDOL = - 1.6 mA VCSN = VCC 0 V < VDO < VCC
Not subject to production test specified by design
- 1.0 - 0.7
Data Input Timing
Not subject to production test - specified by design
Clock period Clock high time Clock low time Clock low before CSN low CSN setup time CLK setup time Clock low after CSN high DI setup time DI hold time Input signal rise time at pin DI, CLK and CSN Input signal fall time at pin DI, CLK and CSN
Version 2.08
tpCLK tCLKH tCLKL tbef tlead tlag tbeh tDISU tDIHO trIN tfIN
1000 500 500 500 500 500 500 250 250 - -
- - - - - - - - - - -
- - - - - - - - - 200 200
ns ns ns ns ns ns ns ns ns ns ns
- - - - - - - - - - -
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Final Datasheet TLE 6263
7.3
Electrical Characteristics (cont'd)
VS = 13.5 V; ICC = 1 mA; normal mode; all outputs open; - 40 C < Tj < 150 C (max. 125C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Data Output Timing
Not subject to production test - specified by design
DO rise time DO fall time DO enable time DO disable time DO valid time
trDO tfDO tENDO tDISDO tVADO
- - - - -
50 50 - - 100
100 100 250 250 250
ns ns ns ns ns
CL = 100 pF CL = 100 pF low impedance high impedance VDO < 0.1 VCC; VDO > 0.9 VCC; CL = 100 pF
Thermal Prewarning and Shutdown (junction temperatures)
Not subject to production test - specified by design
OUTHS thermal prewarning ON temperature OUTHS thermal prewarning hyst. OUTHS thermal shutdown temp. OUTHS thermal switch-on temp. OUTHS thermal shutdown hyst. OUTHS ratio of SD to PW temp.
TjPW
T
120 - 150 120 -
145 30 175 - 30 1.20
170 - 200 170 - - 200
C K C C K - C C
bit 0 of SPI diagnosis word - - - - - hysteresis 15K (typ.) hysteresis 15K (typ.)
TjSD TjSO
T
TjSD / TjPW
Vcc thermal shutdown temp. TjSD OUTHS thermal shutdown temp.
155
185 150
TjSD
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8
Timing Diagrams
CSN High to Low & rising edge of CLK: DO is enabled. Status information is transfered to Output Shift Register
CSN
CSN Low to High: Data from Shift-Register is transfered to e.g. HS-Switch
time
CLK
0
1
2
3
4
5
6
7
0
1
actual Data
new Data
DI
0
1
2
3
4
5
6
7
0 +
1 +
DI: Data will be accepted on the falling edge of CLK-Signal previous Status actual Status
DO
0
1
2
3
4
5
6
7
0
1
DO: State will change on the rising edge of CLK-Signal
eg. OUTHS
old Data
actual Data
Figure 6:
SPI-Data Transfer Timing
Figure 7:
Version 2.08
SPI-Input Timing
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Final Datasheet TLE 6263
Figure 8:
Turn OFF/ON Time
Figure 9:
Version 2.08
DO Valid Data Delay Time and Valid Time
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Figure 10:
DO Enable and Disable Time
tWD tCWmax tCWmin
closed window
tOWmax tOWmin
open window
min. 5.1
max. 7.2
10.0
save trigger area
min. 13.6
max. 18.9
t / ms
Figure 11:
Version 2.08
Watchdog Time-Out Definitions
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Final Datasheet TLE 6263
tCW WD Trigger IBIT 0 tCW tOW
tOW tCW+tOW tLW tLW
tCW
tOW tCW
tLW tCW tOW
Reset Out
tWDR
t
Watchdog timer reset
t
normal operation
timeout (to long)
normal operation
timeout (to short)
normal operation
Figure 12:
Watchdog Timing Diagram
VCC
VRT VINT-Fail
t < tRR
WD Trigger IBIT 0
tRD
tLW
tLW
tCW
tOW
tRD
tLW
tCW
t
t Reset Out tWDR tRR
SPI diagnosis bit 6 VINT-Fail Flag in VStbmode
Watchdog timer reset
t
start up
HIGH
normal operation
tSR
undervoltage
start up
LOW activation by microcontroller
t
Figure 13:
Reset Timing Diagram
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5V C1 C2 C1 R1 R1 RTH CANH CANL RTL SI WK1 WK2 OUTHS 13.5 V 100 nF
RxD TxD 20 pF CSN DO CLK DI INT RO FSO VCC +VS GND VCI 100 nF 22 F
Figure 14:
Test Circuit
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9
Application
Vbat
CAN bus
TLE 6263
26 24
CANH CANL
RxD TxD CSN
2 1
1 k
12 11 10 13
27 25
RTH CLK RTL DO SI OUTHS WK2 WK1 +VS GND
6 - 9; 20 - 23
160 k
16
DI INT RO VCC FSO VCI
P e.g. C505C, C164C
100 k
*)10nF
14 4
28 3 19
1 k
10 k
5
100 nF
17 18
15
22 F
GND
68 F 100 nF
*)
100 nF
only for improvement refer to 6.9)
Figure 15:
Application Circuit
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Final Datasheet TLE 6263
10
Package Outlines
P-DSO-28-18 (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device
Dimensions in mm
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GPS05123
Final Datasheet TLE 6263
Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81669 Munchen (c) Infineon Technologies AG 2001 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Version 2.08
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Infineon goes for Business Excellence
"Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction."
Dr. Ulrich Schumacher
http://www.infineon.com
Published by Infineon Technologies AG

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